1. Field of the Invention
The present invention relates to a semiconductor process. More particularly, the present invention relates to a wafer-level chip package process.
2. Description of Related Art
Compared to the conventional package technology which works with die, wafer-level package (WLP) processes the entire wafer. In other words, compared to the conventional die package, WLP performs back-end package process to a plurality of chip units at the same time. Thus, the chip package process is simplified, and the time and cost of the chip package process are reduced. That is, after the devices, circuits, and the related front-end semiconductor processes on a wafer's surface have been completed, the back-end package process can be directly performed to the entire wafer, and then wafer saw process is performed to form a plurality of chip packages.
In today's developing optoelectronic industry, mature semiconductor manufacturing technologies have been widely applied to optoelectronic devices and the design of optoelectronic devices are continuously going towards minimization and multi-functionality. For example, the typical optoelectronic devices using semiconductor manufacturing process technologies include charge-coupled device (CCD) chip, complementary metal-oxide semiconductor (CMOS) image sensing chip etc. Similarly, the time and cost for mass-manufacturing optoelectronic devices with foregoing wafer-level package process can also be reduced.
FIGS. 1A˜1D are flowcharts illustrating a conventional wafer-level chip package process. The conventional wafer-level chip package process includes the following steps. First, as shown in FIG. 1A, the transparent substrate 110 is disposed on the active surface 120a of the wafer 120, wherein a plurality of chips 122 has been disposed on the active surface 120a of the wafer 120, and the transparent substrate 110 has a chip sealing layer 112 and a transparent layer 114, wherein the chip sealing layer 112 is adhered to the active surface 120a through an adhesive 130. Accordingly, a chamber 140 is formed between the transparent substrate 110 and the active surface 120a of the wafer 120 for protecting the chips 122 from being damaged by external force or contaminated by dust.
Next, as shown in FIG. 1B, the transparent layer 114 is cut by using a cutter 102 to form a first groove 114a. Next, as shown in FIG. 1C, the back surface 120b of the wafer 120 is cut by using another cutter 104 to form a second groove 120c, wherein the second groove 120c corresponds to the first groove 114a, and an appropriate thickness of chip sealing layer 112 is remained between the second groove 120c and the first groove 114a. After that, as shown in FIG. 1D, the transparent substrate 110 and the wafer 120 are singulated to obtain a plurality of chip packages 100.
It should be noted that in the cutting process described above, water is used for cooling the cutters or cleaning the chippings on the wafer produced during the cutting. Thus, during the procedure of cutting the back surface of the wafer to form the second groove, water vapor may seep into the chamber through the interface between the wafer and the chip sealing layer, and further may damage the sealability of the chip package.